High/low speed mode selection for output driver circuits of a memory interface

ABSTRACT

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

Notice: more than one reissue application has been filed for the reissueof U.S. Pat. No. 9,934,169. The reissue applications are applicationSer. Nos. 16/839,573 and 16/838,536 (the present application), both ofwhich are reissues of U.S. Pat. No. 9,934,169. This application is areissue application for U.S. Pat. No. 9,934,169 issued on Apr. 3, 2018on U.S. Ser. No. 15/416,565 filed Jan. 26, 2017, which was acontinuation of U.S. application Ser. No. 14/818,586, filed on Aug. 5,2015, which was a continuation of U.S. application Ser. No. 14/093,916filed Dec. 2, 2013 which claims priority under 35 U.S.C. § 119(e) toU.S. provisional patent application No. 61/732,589 filed on Dec. 3,2012, and under 35 U.S.C. § 119(a) to Korean Patent Application No.10-2013-0028039 filed on Mar. 15, 2013, the entire contents of each ofwhich are hereby incorporated by reference in their entirety, and isco-pending with application Ser. No. 16/839,573, filed on Apr. 3, 2020,which is another reissue application of U.S. Pat. No. 9,934,169.

BACKGROUND

Embodiments of the present inventive concepts relate to a method ofoperating input/output interfaces, and more particularly to a method ofoperating an input/output interface which may select and use one of aplurality of output driver circuits or one of a plurality of inputreceiver circuits.

Each of a system on chip (SoC) including a central processing unit (CPU)and a memory controller and a memory device (e.g., main memory),connected to the SoC includes an input/output interface for interfacingmutual data transmission.

According to an increased operation speed, as a swing width of a datasignal mutually transmitted and received between the SoC and the memorydevice gets decreased, not only an influence of external noise getsincreased, but also impedance mismatching in the input/output interfacemay be a problem. In order to solve the impedance mismatching, theinput/output interface may include an impedance mismatching circuitwhich is referred to as On-Die Termination, On-Chip Termination, orOn-Board Termination.

SUMMARY

According to an example embodiment of the inventive concepts, a methodof operating an input/output interface is provided. The method mayinclude selecting one of a plurality of output driver circuits accordingto a mode selection signal, and outputting a data signal using theselected output driver circuit. The mode selection signal is a controlsignal for controlling an on-die termination (ODT) circuit included inthe input/output interface.

Example embodiments provide that the method may further includegenerating the mode selection signal according to a memory latencybefore the selecting.

Example embodiments provide that the memory latency may be a readlatency or a write latency.

Example embodiments provide that the method may further includegenerating the mode selection signal based on a mode register set (MRS)command before the selecting. The MRS command may be used for adjustingan operation frequency.

Example embodiments provide that the selecting may select one of theplurality of output driver circuits which includes a NMOS pull-uptransistor when the mode selection signal indicates an operation modefor a high speed operation, and one of the plurality of output drivercircuits which includes a PMOS pull-up transistor when the modeselection signal indicates an operation mode for a low speed operation.

Example embodiments provide that the method may further includeselecting one of a plurality of termination levels of the ODT circuitincluded in the input/output interface according to the mode selectionsignal.

Example embodiments provide that the plurality of termination levels mayinclude a supply voltage level, a ground voltage level, and a mediumlevel between the supply voltage level and the ground voltage level.

According to an example embodiment of the inventive concepts, a methodof operating an input/output interface is provided. The method mayinclude selecting one of a plurality of input receiver circuitsaccording to a mode selection signal, and receiving a data signal inputusing the selected input receiver circuit.

Example embodiments provide that the mode selection signal may be acontrol signal for controlling the on-die termination (ODT) circuitincluded in the input/output interface.

Example embodiments provide that the method may further includegenerating the mode selection signal according to memory latency beforethe selecting, and the memory latency may include a read latency andwrite latency.

Example embodiments provide that the method may further includegenerating the mode selection signal based on a mode register set (MRS)command, the MRS command may be used for adjusting a memory operationfrequency before the selecting.

Example embodiments provide that the selecting may select a differentinput receiver circuit when the mode selection signal indicates anoperation mode for a high speed operation and than when the modeselection signal indicates an operation mode for a low speed operation.

Example embodiments provide that the selecting may select at least oneof the plurality of input receiver circuits having a plurality of stageswhen the mode selection signal indicates an operation mode for a highspeed operation.

Example embodiments provide that the selecting may select at least oneof the plurality of input receiver circuits having different types ofMOS transistors when the mode selection signal indicates an operationmode for a low speed operation, the different types of MOS transistorsbeing connected to each other in series.

Example embodiments provide that the method may further includeselecting one of a plurality of sense amplifier flip-flops according tothe mode selection signal.

According to an example embodiment, a method of operating aninput/output interface is provided. The method may include generating amode selection signal based on a received command signal, andcontrolling an on-die termination (ODT) circuit included in theinput/output interface according to the mode selection signal.

Example embodiments provide that a controller of a memory deviceincludes a mode register configured to store operation mode data forcontrolling the memory device, and the operation mode data includesmemory latency data and operation frequency data. The memory latencydata may indicate a memory latency of the memory device. The operationfrequency data may indicate an operation frequency of the memory device.

Example embodiments provide that generating the mode selection signal isfurther based on the operation frequency data.

Example embodiments provide that generating the mode selection signal isfurther based on the memory latency data.

Example embodiment provide that the method may further include selectingone of a plurality of output driver circuits according to the modeselection signal, and outputting a data signal using the selected one ofthe plurality of output driver circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the present generalinventive concepts will become apparent and more readily appreciatedfrom the following description of the embodiments, taken in conjunctionwith the accompanying drawings of which:

FIG. 1 is a block diagram of a memory system according to an exampleembodiment of the inventive concepts;

FIG. 2 is a block diagram according to an example embodiment of a memorydevice illustrated in FIG. 1 ;

FIG. 3 is a block diagram according to an example embodiment of thememory device illustrated in FIG. 1 ;

FIG. 4 is a block diagram according to an example embodiment of a firstinput/output interface illustrated in FIG. 2 ;

FIG. 5 is a circuit diagram according to an example embodiment of anoutput driver block illustrated in FIG. 4 ;

FIG. 6 is a circuit diagram according to another example embodiment ofthe output driver block illustrated in FIG. 4 ;

FIG. 7 is a block diagram according to an example embodiment of theinput receiver block illustrated in FIG. 4 ;

FIG. 8 is an exemplary wave form diagram of a data signal input to theinput receiver block illustrated in FIG. 7 ;

FIG. 9 is a circuit diagram according to an example embodiment of afirst input receiver circuit illustrated in FIG. 7 ;

FIG. 10 is a circuit diagram according to an example embodiment of asecond input receiver circuit illustrated in FIG. 7 ;

FIG. 11 is a circuit diagram according to another example embodiment ofthe second input receiver circuit illustrated in FIG. 7 ;

FIG. 12 is a circuit diagram according to an example embodiment of athird input receiver circuit illustrated in FIG. 7 ;

FIG. 13 is a block diagram according to another example embodiment ofthe input receiver block illustrated in FIG. 4 ;

FIG. 14 is a circuit diagram according to an example embodiment of asense amplifier flip-flop of FIG. 13 ;

FIG. 15 is a circuit diagram according to another example embodiment ofthe sense amplifier flip-flop of FIG. 13 ;

FIG. 16 is a circuit diagram according to an example embodiment of theon-die termination (ODT) circuit of FIG. 4 ;

FIG. 17 is a block diagram according to another example embodiment ofthe first input/output interface of FIG. 2 ;

FIG. 18 is a flowchart of a method of operating an input/outputinterface according to an example embodiment of the inventive concepts;

FIG. 19 is a flowchart of a method of operating an input/outputinterface according to another example embodiment of the inventiveconcepts;

FIG. 20 is a conceptual diagram depicting an example embodiment of apackage including the memory device illustrated in FIG. 1 ;

FIG. 21 is a conceptual diagram depicting tridimensionally an exampleembodiment of the package including the memory device illustrated inFIG. 1 ;

FIG. 22 is a block diagram according to an example embodiment of asystem-in package including the memory system illustrated in FIG. 1 anda non-volatile memory device;

FIG. 23 is a block diagram according to another example embodiment ofthe system-in package including the memory system illustrated in FIG. 1;

FIG. 24 is a block diagram according to an example embodiment of thememory system including the memory device illustrated in FIG. 1 ;

FIG. 25 is a block diagram according to another example embodiment ofthe memory system including the memory device illustrated in FIG. 1 ;

FIG. 26 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 ;

FIG. 27 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 ;and

FIG. 28 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 .

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the size and relative sizes of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first signal could be termed asecond signal, and, similarly, a second signal could be termed a firstsignal without departing from the teachings of the disclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram of a memory system according to an exampleembodiment of the inventive concepts. Referring to FIG. 1 , a memorysystem 10 according to an example embodiment of the inventive conceptsmay include a memory device 100 (e.g., a main memory) and a system onchip (SoC) 200.

According to an example embodiment, the memory system 10 may be embodiedin a mobile application processor (AP); however, a technical scope ofthe inventive concepts is not limited thereto. In various embodiments,the memory system 10 may be embodied in a special purpose AP and/or anyother like AP.

The memory device 100 may include a first internal circuit 110 composingthe inside of the memory device 100 and a first input/output (I/O)interface 120. According to an example embodiment, the memory device 100may be embodied in a dynamic random access memory (DRAM) (e.g.,synchronous DRAM (SDRAM) and the like), and a technical scope of theinventive concepts is not limited thereto.

The first input/output interface 120 may interface a data signal inputor a data signal output between the first internal circuit 110 and theSoC 200. The first internal circuit 110 and the first input/outputinterface 120 are described in detail referring to FIGS. 2 to 19 .

The memory device 100 may be connected to the SoC 200 through a bus 101.The SoC 200 may include a second internal circuit 210 composing theinside of the SoC 200 and a second input/output interface 220.

According to an example embodiment, the second internal circuit 210 mayinclude a central processing unit (CPU) (not shown) for entirelyperforming an operation of the memory system 10, a graphic processingunit (GPU) (not shown), and/or a memory controller (not shown).According to an example embodiment, the second input/output interface220 may be included in the memory controller. A structure of the secondinternal circuit 210 is substantially the same as a structure of thefirst internal circuit 110.

FIG. 2 is a block diagram according to an example embodiment of a memorydevice illustrated in FIG. 1 . Referring to FIGS. 1 and 2 , the firstinternal circuit 110 of the memory device 100 may include a controllogic 130, a refresh counter 132, a row multiplexer 134, a plurality ofrow buffers 136, a plurality of row decoders 138, a bank control logic140, a plurality of column buffers 142, a plurality of column decoders144, a plurality of banks 150, and an input/output gate 154.

The control logic 130 may control each configuration element (e.g., therefresh counter 132, the row multiplexer 134, the bank control logic140, and/or a plurality of column buffers 142) in response to aplurality of signals (a clock signal CK, a command signal CMD, and anaddress signal ADD).

The command signal CMD may denote a combination of a plurality ofcommands (e.g., CS, RAS, CAS, and/or WE). According to an exampleembodiment, the command signal CMD and the address signal ADD may betransmitted from a memory controller (not shown) included in the SoC200.

The control logic 130 may include a command decoder 130-1 and a moderegister 130-2. According to an example embodiment, the command decoder130-1 and/or the mode register 130-2 may be separately embodied outsidethe control logic 130. The command decoder 130-1 may decode a commandsignal CMD configured to have a plurality of signals (e.g., CS, RAS,CAS, and/or WE) based on a clock signal CK, and generate a command forcontrolling each configuration element (e.g., the refresh counter 132,the row multiplexer 134, the bank control logic 140, and/or theplurality of column buffers 142) according to a result of the decoding.

According to an example embodiment, the command decoder 130-1 may decodethe command signal CMD, and generate a command for performing varioustypes of operations (e.g., a read operation, a write operation, and/or arefresh operation).

The mode register 130-2 stores data for controlling various operationmodes of the memory device 100. According to an example embodiment, themode register 130-2 may store data about a memory latency of the memorydevice 100, data about an operation frequency, and/or data necessary fora control of the on-die termination (ODT) circuit (not shown).

The refresh counter 132, in response to a refresh command output fromthe command decoder 130-1, may generate a row address corresponding tothe refresh command.

The row multiplexer 134 may select one of a row address generated by therefresh counter 132 and a row address output from the control logic 130in response to a selection signal (not shown). According to an exampleembodiment, when a refresh operation is performed, the row multiplexer134 may select a row address generated by the refresh counter 132.According to another example embodiment, when a normal memory accessoperation (e.g., a read operation or a write operation), is performed,the row multiplexer 134 may select a row address output from the controllogic 130.

Each of the plurality of row decoders 136 may buffer a row addressoutput from the row multiplexer 134. According to an example embodiment,the plurality of row decoders 138 may be embodied in a row decoder;however, example embodiments are not limited thereto.

A row decoder corresponding to a bank selected by the bank control logic140 among the plurality of row decoders 138 may decode a row addressoutput from a row buffer corresponding to the bank among the pluralityof row buffers 136. According to an example embodiment, the plurality ofrow decoders 138 may be embodied in a row decoder; however, exampleembodiments are not limited thereto.

The bank control logic 140 may select at least one of the plurality ofbanks 150 according to a control signal and/or command of the controllogic 130.

Each of the plurality of column buffers 142 may buffer a column addressoutput from the control logic 130. According to an example embodiment,the plurality of column buffers 142 may be embodied in one columnbuffer; however, example embodiments are not limited thereto. A columndecoder corresponding to a bank selected by the bank control logic 140among the plurality of column decoders 144 may decode a column addressoutput from a column buffer corresponding to the bank among theplurality of column buffers 142.

According to an example embodiment, the plurality of column decoders 144may be embodied in one column decoder; however, example embodiments arenot limited thereto.

Each of the plurality of banks 150 each labeled as Bank0 to BankN mayinclude a memory cell array 151 and a sense amplifiers & write driverblock 152.

For convenience of description, it is illustrated that each of theplurality of banks 150 is embodied in different layers; however, thescope of the inventive concepts should not be limitedly interpreted by astructure and layout of the plurality of banks 150.

The memory cell array 151 includes a plurality of word lines (or rowlines), a plurality of bit lines (or column lines), and a plurality ofmemory cells for storing data.

The sense amplifiers & write driver block 152, when the memory device100 perform a read operation, may operate as a sense amplifier sensingand amplifying a voltage change of each bit line. The sense amplifiers &write driver block 152, when the memory device 100 performs a writeoperation, may operate as a write driver which may drive each of theplurality of bit lines included in the memory cell array 151.

The input/output gate 154 may transmit data signals output from thesense amplifiers & write driver block 152 to the first input/outputinterface 120 in response to a column selection signal output from oneof the plurality of column decoders 144. According to an exampleembodiment, the input/output gate 154 may transmit data signals inputthrough the first input/output interface 120 to the sense amplifiers &write driver block 152 in response to the column selection signal.

According to an example embodiment, the input/output gate 154 may beincluded in the first input/output interface 120. The first input/outputinterface 120 may be controlled by a mode selection signal MSELtransmitted from the control logic 130. According to an exampleembodiment, circuits included in the first input/output interface 120may be selectively used according to the mode selection signal MSEL.

According to an example embodiment, the mode selection signal MSEL maybe generated by the control logic 130 based on data for controllingoperation modes of the memory device 100 stored in the mode register130-2. According to another example embodiment, the mode selectionsignal MSEL may be generated by the control logic 130 based on dataabout a memory latency stored in the mode register 130-2. The memorylatency may be read latency or write latency.

According to an example embodiment, the mode selection signal MSEL maybe generated by the control logic 130 based on data about an operationfrequency stored in the mode register 130-2. According to still anotherexample embodiment, the mode selection signal MSEL may be generated bythe control logic 130 based on a mode register set (MRS) command foradjusting an operation frequency.

According to an example embodiment, the mode selection signal MSEL maybe a control signal for controlling an ODT circuit (not shown) generatedby the control logic 130. In this case, the first internal circuit 110may further include an anti-fuse (not shown) for storing information forcontrolling the ODT circuit.

According to an example embodiment, the memory device 100 may include aseparate unit (not shown) for generating a mode selection signal (MSEL).The first input/output interface 120 will be described in detailreferring to FIG. 4 .

FIG. 3 is a block diagram according to another example embodiment of thememory device illustrated in FIG. 1 . Referring to FIGS. 1 to 3 , amemory device 100′ 100-2 according to another example embodiment of thememory device 100 illustrated in FIG. 1 is different from the memorydevice 100 of FIG. 2 in a transmission path of the mode selection signalMSEL.

The mode selection signal MSEL may be transmitted to the firstinput/output interface 120 from the SoC 200, e.g., a memory controller(not shown) included in the SoC 200, to the first input/output interface120. According to an example embodiment, the SoC 200 may transmit acontrol signal for controlling the on-die termination (ODT) circuitincluded in the first input/output interface 120 to the memory device100′ 100-2, and the control signal may be input to the firstinput/output interface 120 as the mode selection signal MSEL.

FIG. 4 is a block diagram according to an example embodiment of a firstinput/output interface illustrated in FIG. 2 . Referring to FIGS. 1, 2,and 4 , a first input/output interface 120A according to an exampleembodiment of the first input/output interface 120 illustrated in FIG. 2may include an output driver (TX) block 160, an input receiver (RX)block 162, an ODT circuit 164, an interface control circuit 166, and aninput/output (I/O) pad 168.

The output driver 160 may output a data signal transmitted from theinput/output gate 154 to the outside of the memory device 100, e.g., theSoC 200, through the input/output pad 168. The output driver block 160may include a plurality of output driver circuits, and this will bedescribed referring to FIGS. 5 and 6 .

The input receiver block 162 may receive and transmit a data signalinput from the outside of the memory device 100 to the input/output gate154 through the input/output pad 168. The input receiver block 162 mayinclude a plurality of input receivers, and this will be describedreferring to FIGS. 7 to 12 .

The ODT circuit 164 may be included in the first input/output interface120A so as to solve impedance mismatching which may occur whenoutputting a data signal to the second input/output interface 220 orinputting the data signal from the second input/output interface 220.

The ODT circuit 164 in FIG. 4 is illustrated inside the firstinput/output interface 120A; however, the ODT circuit 164 may beembodied outside of the first input/output interface 120A or outside thememory device 100; and the technical scope of the inventive concepts arenot limited by layout of the ODT circuit 164. The ODT circuit 164 willbe described in detail referring to FIG. 16 .

FIG. 5 is a circuit diagram according to an example embodiment of anoutput driver block illustrated in FIG. 4 .

Referring to FIGS. 2, 4, and 5 , an output driver block 160A accordingto an example embodiment of the output driver block 160 illustrated inFIG. 4 may include a pre-driver circuit 160A-1, a plurality of outputdriver circuits 160A-2 and 160A-3, and a plurality of switches SWT1 andSWT2.

The pre-driver circuit 160A-1 may receive a data signal transmitted fromthe input/output gate 154, and generate a plurality of pull-up signalsPU1 and PU2 and a plurality of pull-down signals PD1 and PD2 based onthe data signal.

A first output driver circuit 160A-2 may include a PMOS pull uptransistor TXTR1 operating according to a first pull-up signal PU1 and aNMOS pull down transistor TXTR2 operating according to a first pull-downsignal PD1. The first output driver circuit 160A-2 may output an outputdata signal DOUT1 based on the first pull-up signal PU1 and the firstpull-down signal PD1.

The second output driver circuit 160A-3 may include a NMOS pull-uptransistor TXTR3 operating according to a second pull-up signal PU2 anda NMOS pull-down transistor TXTR4 operating according to a secondpull-down signal PD2. The second output driver circuit 160A-3 may outputan output data signal DOUT2 based on the second pull-up signal PU2 andthe second pull-down signal PD2.

An interface control circuit 166 may generate selection signals TXSEL1and TXSEL2 based on the mode selection signal MSEL. Each of switchesSWT1 and SWT2 may be switched by each of the selection signals TXSEL1and TXSEL2 output from the interface control circuit 166. According toan example embodiment, when the mode selection signal MSEL indicates anoperation mode for a high speed operation, a first switch SWT1 may beturned off by the first selection signal TXSEL1 and a second switch SWT2may be turned on by the second selection signal TXSEL2.

According to another example embodiment, when the mode selection signalMSEL indicates an operation mode for a low speed operation, the firstswitch SWT1 may be turned on by the first selection signal TXSEL1 andthe second switch SWT2 may be turned off by the second selection signalTXSEL2. That is, the first output driver circuit 160A-2 including thePMOS pull-up transistor TXTR1 may be used in an operation mode for a lowspeed operation, and the second output driver circuit 160A-3 includingthe NMOS pull-up transistor TXTR3 may be used in an operation mode for ahigh speed operation.

According to an example embodiment, each of the first pull up signal PU1and the second pull-up signal PU2 may be a signal the same as the firstselection signal TXSEL1 or the second selection signal TXSEL2, or asignal generated based on the first selection signal TXSEL1 or thesecond selection signal TXSEL2. The first pull-up signal PU1 and thesecond pull-up signal PU2 may have the same phase or opposite phase.According to another example embodiment, the pre-driver circuit 160A-1may further include a phase inversion circuit so that the first pull-upsignal PU1 and the second pull-up signal PU2 may have opposite phases.

FIG. 6 is a circuit diagram according to another example embodiment ofthe output driver block illustrated in FIG. 4 . Referring to FIGS. 4 to6 , an output driver block 160B according to another example embodimentof the output driver block 160 illustrated in FIG. 4 may include apre-driver circuit 160B-1 and a plurality of output driver circuits160B-2 and 160B-3.

The pre-driver circuit 160B-1 may receive a data signal transmitted fromthe input gate 154 and generate a plurality of pull-up signals PU3 andPU4 and a pull down signal PD3 based on the data signal.

A first output driver circuit 160B-2 is substantially the same as thefirst output driver circuit 160A-2 of FIG. 5 , and a second outputdriver circuit 160B-3 is substantially the same as the second outputdriver circuit 160A-3 of FIG. 5 . The first output driver circuit 160B-2and the second output driver circuit 160B-3 commonly use a NMOSpull-down transistor TXTR7.

The interface control circuit 166 may generate output driver selectionsignals TXSEL3 and TXSEL4 based on the mode selection signal MSEL.

Each of the switches SWT3 and SWT4 may be switched by each of the outputdriver selection signals TXSEL3 and TXSEL4 output from the interfacecontrol circuit 166.

According to an example embodiment, when the mode selection signal MSELindicates an operation mode for a high speed operation, a third switchSWT3 may be turned off by the third output driver selection signalTXSEL3, and a fourth switch SWT4 may be turned on by the fourth outputdriver selection signal TXSEL4.

According to an example embodiment, when the mode selection signal MSELindicates an operation mode for a low speed operation, the third switchSWT3 may be turned on by the third output driver selection signalTXSEL3, and the fourth switch SWT4 may be turned off by the fourthoutput driver selection signal TXSEL4. That is, the first output drivercircuit 160B-2 including a PMOS pull-up transistor TXTR5 may be used inan operation mode for a low speed operation, and the second outputdriver circuit 160B-3 including a NMOS pull-up transistor TXTR6 may beused in an operation mode for a high speed operation.

According to an example embodiment, each of a third pull-up signal PU3and a fourth pull-up signal PU4 may be a signal the same as the thirdselection signal TXSEL3 or the fourth selection signal TXSEL4, or asignal generated based on the third selection signal TXSEL3 or thefourth selection signal TXSEL4. The third pull-up signal PU3 and thefourth pull-up signal PU4 may have the same phase or opposite phases.

According to an example embodiment, the pre-driver circuit 160B-1 mayfurther include a phase inversion circuit so that the third pull-upsignal PU3 and the fourth pull-up signal PU4 may have opposite phases.

FIG. 7 is a block diagram according to an example embodiment of theinput receiver block illustrated in FIG. 4 . Referring to FIGS. 4 and 7, the input receiver block 162 may include a plurality of switches SWR1to SWR3 and a plurality of input receiver circuits 170, 172, and 174.

The interface control circuit 166 may generate a plurality of inputreceiver selection signals RXSEL1 to RXSEL3 according to the modeselection signal MSEL. Each of the switches SWR1 to SWR3 may select oneof the input receiver circuits 170, 172, and 174 according to each ofthe input receiver selection signals RXSEL1 to RXSEL3.

According to an example embodiment, a first input receiver circuit 170may have a structure suitable for an operation mode for a high speedoperation, a second input receiver circuit 172 may have a structuresuitable for an operation mode for an intermediate speed operation, anda third input receiver circuit 174 may have a structure suitable for anoperation mode for a low speed operation.

That is, when the mode selection signal MSEL indicates an operation modefor a high speed operation, the first switch SWR1 may be turned onaccording to the first input receiver selection signal RXSEL1, and eachof the remaining switches SWR2 and SWR3 may be turned off according toeach of the input receiver selection signals RXSEL2 and RXSEL3.

In the same manner, the second input receiver 172 may be selected in anoperation mode for an intermediate speed operation, and the third inputreceiver 174 may be selected in an operation mode for a low speedoperation.

The first input receiver circuit 170, the second input receiver 172, orthe third input receiver 174 may receive an input data signal DINtransmitted from the input/output pad 168, and output a first receivingdata signal RO1, a second receiving data signal RO2, or a thirdreceiving data signal RO3 based on the received input data signal DIN.

According to an example embodiment, the input receiver block 162 mayinclude only two of the input receiver circuits 170, 172, and 174.According to another example embodiment, the input receiver block 162may further include input receiver circuits (not shown) in addition tothe input receiver circuits 170, 172, and 174. In this case, the inputreceiver block 162 may selectively use one of four or more inputreceiver circuits.

A structure of each of the input receiver circuits 170, 172, and 174will be described in detail referring to FIGS. 8 to 12 .

FIG. 8 is an exemplary wave form diagram of a data signal input to theinput receiver block illustrated in FIG. 7 . Referring to FIGS. 7 and 8, with respect to an input data signal DIN1 having a high frequency andwhose signal level swings near a ground voltage level VSSQ, the firstinput receiver 170 may be selected and used.

With respect to an input data signal DIN2 having an intermediatefrequency and whose signal level swings near a supply voltage levelVDDQ, the second input receiver 172 may be selected and used. Withrespect to an input data signal DIN3 whose frequency is low and whosesignal level largely swings between the ground voltage level VSSQ andthe supply voltage level VDDQ, the third input receiver 174 may beselected and used.

FIG. 9 is a circuit diagram according to an example embodiment of afirst input receiver circuit illustrated in FIG. 7 . Referring to FIGS.7 and 9 , the first input receiver circuit 170 may have a structurehaving a plurality of stages (e.g., at least two stages).

For convenience of description in FIG. 9 , a structure in which thefirst input receiver circuit 170 has two stages is illustrated; however,a scope of a right of the inventive concepts should not be limitedlyinterpreted by the number of stages.

A first stage 170-1 outputs data signals DO1 and DO2 based on the inputdata signal DIN which is input and a reference voltage signal VREF. Asecond stage 170-2 may transmit the receiving data signal RO1 to theinput/output gate 154 based on the data signals DO1 and DO2 output fromthe first stage 170-1.

As illustrated in FIG. 9 , each of the first stage 170-1 and a secondstage 170-2 may be embodied in a P-type differential amplifier; however,example embodiments of the structure of the first input receiver circuit170 are not limited thereto. For example, the second stage 170-2 may beembodied in a N-P type differential amplifier instead of a P typedifferential amplifier. An exemplary structure of the N-P typedifferential amplifier is illustrated in FIG. 11 .

FIG. 10 is a circuit diagram according to an example embodiment of asecond input receiver circuit illustrated in FIG. 7 . Referring to FIGS.7 and 10 , a second input receiver circuit 172A according to an exampleembodiment of the second input receiver circuit 172 illustrated in FIG.7 may output a receiving data signal RO2 based on the input data signalDIN and the reference voltage signal VREF.

FIG. 11 is a circuit diagram according to another example embodiment ofthe second input receiver circuit illustrated in FIG. 7 . Referring toFIGS. 7 and 11 , a second input receiver circuit 172B according toanother example embodiment of the second input receiver circuit 172illustrated in FIG. 7 may be embodied in a N-P type differentialamplifier configured to have a combination of a N type differentialamplifier 172B-1 and a P type differential amplifier 172B-2.

The input data signal DIN and the reference voltage signal VREF areinput to each of the N type differential amplifier 172B-1 and P typedifferential amplifier 172B-2. The second receiver circuit 172B mayoutput a receiving data signal RO2 based on the input data signal DINand the reference voltage signal VREF which are input. The second inputreceiver circuit 172A or 172B may be embodied in the N type differentialamplifier or the N-P type differential amplifier; however, a structureof the second input receiver circuit 172 is not limited thereto.

FIG. 12 is a circuit diagram according to an example embodiment of athird input receiver circuit illustrated in FIG. 7 . Referring to FIGS.7 and 12 , a third input receiver circuit 174 may be embodied in a CMOSinverter including different types of MOS transistors which areconnected in series.

The third input receiver circuit 174 may receive the input data signalDIN and output a receiving data signal RO3 based on the received inputdata signal DIN.

FIG. 13 is a block diagram according to another example embodiment ofthe input receiver block illustrated in FIG. 4 . FIG. 14 is a circuitdiagram according to an example embodiment of a sense amplifierflip-flop of FIG. 13 . FIG. 15 is a circuit diagram according to anotherexample embodiment of the sense amplifier flip-flop of FIG. 13 .Referring to FIGS. 4 and 13 , an input receiver block 162′ according toanother example embodiment of the input receiver block 162 of FIG. 4 mayinclude switches SWR4 and SWR5, a fourth input receiver circuit 176, andsense amplifier flip-flops 178-1 and 178-2.

The interface control circuit 166 may generate a plurality of inputreceiver selection signals RXSEL4 and RXSEL5 according to the modeselection signal MSEL. For example, the interface control circuit 166may generate the plurality of input receiver selection signals RXSEL4and RXSEL5 according to the mode selection signal MSEL includinginformation on a level and/or a frequency of the input data signal DIN.

Each of the switches SWR4 and SWR5 may select a transmission path of theinput data signal according to each of the input receiver selectionsignals RXSEL4 and RXSEL5.

When a fourth switch SWR4 is turned on, a fifth switch SWR5 may beturned off, and when the fourth switch SWR4 is turned off, a fifthswitch SWRS may be turned on.

According to an example embodiment, when the fourth switch SWR4 isturned on, the input data signal DIN may be output as a fourth receivingdata signal RO4 through the fourth input receiver circuit 176 and asecond sense amplifier flip-flop 178-2. According to another exampleembodiment, when the fifth switch SWR5 is turned on, the input datasignal DIN may be output through a first sense amplifier flip-flop 178-1as the fifth receiving data signal RO5.

The fourth input receiver circuit 176 may be embodied in the first inputreceiver circuit 170 of FIG. 9 , the second input receiver 172A of FIG.10 , the second input receiver circuit 172B of FIG. 11 , or the thirdinput receiver circuit 174 of FIG. 12 .

Each of the sense amplifier flip-flops 178-1 and 178-2 may sample theinput data signal DIN based on a sampling strobe signal SSTR of FIG. 14or 15 . The sampling strobe signal SSTR may widely denote a clock signalused so as to sample the input data signal DIN. For example, a datastrobe signal DQS may be used as a sampling strobe signal SSTR.

The sampled input data signal DIN may be output to an input/output gate154 as the fourth receiving data signal RO4 or the fifth receiving datasignal RO5.

Referring to FIG. 14 , a first sense amplifier flip-flop 178-1Aaccording to an example embodiment of the first sense amplifierflip-flop 178-1 (e.g., P type sense amplifier flip-flop), isillustrated. According to an example embodiment, a second senseamplifier flip-flop 178-2 may have a structure the same as the firstamplifier flip-flop 178-1A.

The input data signal DIN may be sampled based on the reference voltagesignal VREF which is a reference of comparison with the input datasignal DIN and a sampling strobe signal SSTR which is a reference ofsampling. According to a result of the sampling, the fifth receivingdata signal RO5 may be output.

Referring to FIG. 15 , a first sense amplifier flip-flop 178-1Baccording to another example embodiment of the first sense amplifierflip-flop 178-1 (e.g., N type sense amplifier flip-flop), isillustrated. According to an example embodiment, the second senseamplifier flip-flop 178-2 may have the same structure as the first senseamplifier flip-flop 178-1B.

The input data signal DIN may be sampled based on the reference voltagesignal VREF which is a reference of comparison with the input datasignal DIN and a sampling strobe signal SSTR which is a reference ofsampling. According to a result of the sampling, the fifth receivingdata signal R05 may be output. According to an example embodiment, whena buffer circuit (not shown) including a plurality of inverters isconnected between the fourth input receiver circuit 176 and the secondsense amplifier flip-flop 178-2, the input data signal DIN at a highvoltage level may be input to the second sense amplifier flip-flop178-2. In this case, the second sense amplifier flip-flop 178-2 may havea structure the same as the N type sense amplifier flip-flop (e.g., thefirst sense amplifier flip-flop 178-1B of FIG. 15 ).

FIG. 16 is a circuit diagram according to an example embodiment of theon-die termination (ODT) circuit of FIG. 4 . Referring to FIGS. 4 and 16, the ODT circuit 164 includes a plurality of branches B1 to Bn, where nis a natural number. A branch B1 includes a first switch SWD1, a firstresistance RS1, a second resistance RS2, and a second switch SWS1.

According to an example embodiment, the first switch SWD1 may beembodied in a PMOS transistor, and the second switch SWS1 may beembodied in a NMOS transistor.

A termination resistance 184 may have a resistance value according to acombination of a plurality of resistances RD1 to RDn and RS1 to RSn aseach of the plurality of switches SWD1 to SWDn and SWS1 to SWSn, where nis a natural number, is switched. A VDDQ termination switch array 180may include a plurality of switches SWD1 to SWDn.

Each of the plurality of switches SWD1 to SWDn included in a VDDQtermination switch array 180 may be turned on or turned off in responseto each of the ODT selection signals ODSEL1 to ODSELn output from theinterface control circuit 166. The VSSQ termination switch array 182 mayinclude a plurality of switches SWS1 to SWSn.

Each of the plurality of switches SWS1 to SWSn included in the VSSQtermination switch array 182 may be turned on or off in response to eachof the ODT selection signals OSSEL1 to OSSELn output from the interfacecontrol circuit 166.

The ODT circuit 164 may have various resistance values of thetermination resistance 184 according to the ODT selection signals ODSEL1to ODSELn and OSSEL1 to OSSELn.

According to an example embodiment, when the mode selection signal MSELindicates an operation mode for a high speed operation, the ODT circuit164 may be terminated at a ground voltage level VSSQ. That is, only aportion of the switches SWS1 to SWSn may be turned on.

According to an example embodiment, when the mode selection signal MSELindicates an operation mode for a low speed operation, according to theODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn, the ODTcircuit 164 may be terminated at a supply voltage level VDDQ. That is,only a portion of the switches SWD1 to SWDn may be turned on.

According to an example embodiment, when the mode selection signal MSELindicates an operation mode for a low speed operation, according to theODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn, theswitches SWD1 to SWDn and SWS1 to SWSn of the ODT circuit 164 may be allturned off. That is, the termination resistance 184 may not be used inthe operation mode for a low speed operation. According to still anotherexample embodiment, a portion of the switches SWD1 to SWDn and a portionof the switches SWS1 to SWSn may be turned on together, and in this casethe ODT circuit 164 may be embodied in a center tap termination (CTT).

FIG. 17 is a block diagram according to another example embodiment ofthe first input/output interface of FIG. 2 . Referring to FIGS. 2, 4,and 17 , in the first input/output interface 120B according to anotherexample embodiment of the first input/output interface 120 illustratedin FIG. 2 , an output driver block (160 of FIG. 4 ) and the ODT circuit(164 of FIG. 4 ) may be embodied in an output driver and ODT block (160′of FIG. 17 ).

The output driver and ODT block 160′ may operate like the output driverblock 160 when the memory device 100 outputs a data signal, and operatelike the ODT circuit 164 when the memory device 100 receives a datasignal. That is, the first input/output interface 120B may not includean additional ODT circuit 164 as illustrated in FIG. 4 and use an outputdriver as the ODT circuit.

According to an example embodiment, the input receiver block 162 of FIG.4 and the ODT circuit 164 of FIG. 4 may be combined and embodied in oneblock. In this case, the block may operate like the ODT circuit 164 whenthe memory device 100 outputs a data signal, and operate like the inputreceiver block 162 when the memory device 100 receives a data signal.

FIG. 18 is a flowchart of a method of operating an input/outputinterface according to an example embodiment of the inventive concepts.Referring to FIGS. 4 to 6, and 18 , in operation S10, the output driverblock 160A and/or 160E selects one of a plurality of output drivercircuits 160A-2, 160A-3, or 160B-2 and 160B-3.

According to an example embodiment, the output driver block 160A and/or160B may select the one output driver circuit 160A-2 or 160A-3, 160B-2or 160B-3 according to an output driver selection signal TXSEL1 toTXSEL4 generated by the interface control circuit 166 based on the modeselection signal MSEL. Then as shown in operation S12, the output driverblock 160A or 160B outputs a data signal DOUT1 or DOUT2 using theselected output driver circuit 160A-2, 160A-3, 160B-2, or 160B-3.

FIG. 19 is a flowchart of a method of operating an input/outputinterface according to another example embodiment of the inventiveconcepts. Referring to FIGS. 7 and 19 , in operation S20, the inputreceiver block 162 selects one of the plurality of input receivercircuits 170, 172, and 174 included in the input receiver block 162.

According to an example embodiment, the input receiver block 162,according to an input receiver selection signal RXSEL1 to RXSEL3generated by the interface control circuit 166, may select the one inputreceiver circuit 170, 172, or 174 based on the mode selection signalMSEL. Then as shown in operation S22, the input receiver block 162receives a data signal RO1 to RO3 using the selected input receivercircuit 170, 172, or 174.

FIG. 20 is a conceptual diagram depicting an example embodiment of apackage including the memory device illustrated in FIG. 1 . Referring toFIGS. 1 and 20 , a package 300 may include a plurality of semiconductordevices 330, 340, and 350 sequentially stacked on the package substrate310. Each of the plurality of semiconductor devices 330 to 350 may bethe memory device 100.

The package 300 may be embodied in a Package on Package (PoP), Ball GridArrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier(PLCC), Plastic Dual In-Line Package (PDIP), Chip On Board (COB),CERamic Dual In-Line Package (CERDIP), plastic metric quad flat pack(MQFP), Thin Quad Flat Pack (TQFP), small-outline integrated circuit(SOIC), shrink small outline package (SSOP), thin small outline (TSOP),system in package (SIP), multi-chip package (MCP), wafer-level package(WLP), wafer-level processed stack package (WSP), or other likepackages.

According to an example embodiment, a memory controller (not shown) maybe embodied in one or more semiconductor device among a plurality ofsemiconductor devices 330 to 350, and embodied on a package substrate310.

For an electrical connection between the plurality of semiconductordevices 330 to 350, electrical vertical connection means (e.g.,Through-silicon via (TSV)), may be used.

The package 300 may be embodied in a hybrid memory cube (hereinafter,“HMC”) of a structure where a memory controller and a memory cell arraydie are stacked. Embodiment in HMC may reduce power consumption andmanufacturing cost by performance improvement of a memory device due toan increase in bandwidth and minimization of an area occupied by amemory device.

FIG. 21 is a conceptual diagram depicting an example embodiment of thepackage including the memory device illustrated in FIG. 1 . Referring toFIGS. 1, 20, and 21 , a package 300′ includes a plurality of dies 330 to350 of a stack structure where each is connected to each other througheach TSV 360.

FIG. 22 is a block diagram according to an example embodiment of asystem-in package including the memory system illustrated in FIG. 1 anda non-volatile memory device. FIG. 23 is a block diagram according toanother example embodiment of the system-in package including the memorysystem illustrated in FIG. 1 .

Referring to FIGS. 1 and 22 , the SoC 200 and a memory device 100 (e.g.,a main memory), may be packaged in a system-in package (SiP) 250. TheSoC 200 may be connected to a non-volatile memory device 400.

According to an example embodiment, the non-volatile memory device 400may be embodied in an electrically erasable programmable read-onlymemory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfertorque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM(FeRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotubeRRAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), aholographic memory, a molecular electronics memory device, an insulatorresistance change memory, and/or other like memory devices; however, thescope of the inventive concepts are not limited thereto.

Referring to FIGS. 1 and 23 , a memory device 100, the SoC 200, and thenon-volatile memory device 400 may be packaged in a SiP 250′.

FIG. 24 is a block diagram according to an example embodiment of thememory system including the memory device illustrated in FIG. 1 .Referring to FIGS. 1 and 24 , a memory system 500 may be embodied in apersonal computer (PC), a tablet PC, or a mobile computing device.

The memory system 500 includes a main board 540, a slot 520 mounted onthe main board 540, a memory module 510 which may be inserted to theslot 520, a chipset 530 which may control an operation of a plurality ofmemory devices 100-1 to 100-m mounted on the memory module 510 throughthe slot 520, a processor 550 which may communicate with the a pluralityof various memory devices 100-1 100, 100-2, to 100-m. Each of theplurality of various memory devices 100-1 100, 100-2, to 100-m may bethe memory device 100 illustrated in FIG. 1 .

For convenience of description in FIG. 24 , there is illustrated onlyone memory module 510; however, the memory system 500 includes at leastone or more memory module.

The chipset 530 is used to transmit or receive data, an address, orcontrol signals between the processor 550 and the memory module 510. Thechipset 530 includes a memory controller 535 for controlling theplurality of memory devices 100-1 to 100-m.

FIG. 25 is a block diagram according to another example embodiment ofthe memory system including the memory device illustrated in FIG. 1 .Referring to FIGS. 1 and 25 , a system 600 may be embodied in anelectronic device or a portable device. The portable device may beembodied in a cellular phone, a smart phone, or a tablet PC.

The system 600 includes a processor 611 and a memory device 613. Thememory device 613 may be the memory device of FIG. 1 . According to anexample embodiment, the processor 611 and the memory device 613 may bepackaged in a package 610. In this case, the package 610 may be mountedon a system board (not shown). The package 610 may denote the package300 illustrated in FIG. 20 , or the package 300′ illustrated in FIG. 21.

The processor 611 includes a memory controller 615 which may control adata processing operation of the memory device 613 (e.g., a writeoperation or a read operation). The memory controller 615 may becontrolled by the processor 611 entirely controlling an operation of thesystem 600. According to an example embodiment, the memory controller615 may be connected between the processor 611 and the memory device613.

Data stored in the memory device 613 may be displayed through a display620 according to a control signal and/or command of the processor 611.

A radio transceiver 630 may transmit or receive a radio signal throughan antenna ANT. For example, the radio transceiver 630 may convert aradio signal received through the antenna ANT into a signal which theprocessor 611 may process. Accordingly, the processor 611 may process asignal output from the radio transceiver 630, store the processed signalin the memory device 613 or display the processed signal through thedisplay 620.

The radio transceiver 630 may convert a signal output from the processor611 into a radio signal, and output the converted radio signal tooutside through the antenna ANT.

An input device 640, as a device which may input a control signal forcontrolling an operation of the processor 611 or data to be processed bythe processor 611, may be embodied in a pointing device such as a touchpad and a computer mouse, a keypad, or a keyboard.

The processor 611 may control the display 620 so that data output fromthe memory device 613, a radio signal output from the radio transceiver630, or data output from the input device 640 may be displayed throughthe display 620.

FIG. 26 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 .Referring to FIGS. 1 and 26 , a system 700 may be embodied in a personalcomputer (PC), a tablet PC, a net-book, an e-reader, a personal digitalassistant (PDA), a portable multimedia player (PMP), a MP3 player, or aMP4 player.

The system 700 includes a processor 711 for entirely controlling anoperation of the system 700 and a memory device 713. The memory device713 may denote the memory device 100 illustrated in FIG. 1 . Accordingto an example embodiment, the processor 711 and the memory device 713may be packaged in a package 710. The package 710 may be mounted on asystem board (not shown). The package 710 may denote the package 300illustrated in FIG. 20 or the package 300′ illustrated in FIG. 21 .

The processor 711 may include a memory controller 715 controlling anoperation of the memory device 713. The processor 711 may display datastored in the memory device 713 through the display 730 according to aninput signal generated by the input device 720. For example, the inputdevice 720 may be embodied in a pointing device such as a touch pad or acomputer mouse, a keypad, or a keyboard.

FIG. 27 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 .Referring to FIGS. 1 and 27 , a system 800 may be embodied in a digitalcamera or a portable device attached to the digital camera.

The system 800 includes a processor 811 entirely controlling anoperation of the system 800 and a memory device 813. Here, the memorydevice 813 may denote the memory device 100 of FIG. 1 . The processor811 may include a memory controller 815 controlling an operation of thememory device 813.

According to an example embodiment, the processor 811 and the memorydevice 813 may be packaged in a package 810. The package 810 may bemounted on a system board (not shown). The package 810 may denote thepackage 300 illustrated in FIG. 20 or the package 300′ illustrated inFIG. 21 .

An image sensor 820 of the system 800 converts an optical image into adigital signal, and the converted digital signal is stored in the memorydevice 813 under a control of the processor 811 or displayed through thedisplay 830. In addition, the digital signal stored in the memory device813 is displayed through the display 830 under a control of theprocessor 811.

FIG. 28 is a block diagram according to still another example embodimentof the memory system including the memory device illustrated in FIG. 1 .A channel 901 may denote optical connection means. The opticalconnection means may denote an optical fiber, an optical waveguide, or amedium transmitting an optical signal.

Referring to FIGS. 1 and 28 , a system 900 may include a first system1000 and a second system 1100. The first system 1000 may include a firstmemory device 100a 100 and an electric-photo conversion circuit 1010.The electric-photo conversion circuit 1010 may convert an electricalsignal output from the first memory device 100a 100 into a photo signal,and output the converted photo signal to the second system 1100 throughoptical connection means 901.

The second system 1100 includes a photoelectric conversion circuit 1120and a second memory device 100b 100-2. The photoelectric conversioncircuit 1120 may convert a photo signal input through the opticalconnection means 901 into an electric signal, and transmit the convertedelectrical signal to the second memory device 100b 100-2.

The first system 1000 may further include the photo-electric conversioncircuit 1020, and the second system 1100 may further include theelectric-photo conversion circuit 1110.

When the second system 1100 transmits data to the first system 1000, theelectric-photo conversion circuit 1110 may convert an electrical signaloutput from the second memory device 100b 100-2 into a photo signal, andoutput the converted photo signal to the first system through theoptical connection means 901. The photoelectric conversion circuit 1020may convert a photo signal input through the optical connection means901 into an electric signal, and transmit the converted electricalsignal to the first memory device 100a 100. A structure and an operationof each memory device 100a 100 and 100b 100-2 are substantially the sameas a structure and an operation of the memory device 100 of FIG. 1 .

A method according to an example embodiment of the inventive concepts,by selecting and using an output driver circuit or an input receivercircuit according to an operation mode, may embody an appropriateinput/output interface in the operation mode.

The method according to an example embodiment of the inventive concepts,by selecting and using the appropriate output driver circuit or an inputreceiver circuit in an operation mode, may improve efficiency inelectricity and maintain good property of a transmission signal.

Although a some example embodiments of the inventive concepts have beenshown and described, it will be appreciated by those skilled in the artthat changes may be made in these embodiments without departing from theprinciples and spirit of the inventive concepts, the scope of which isdefined in the appended claims and their equivalents.

What is claimed is:
 1. An input/output interface for a memory devicecomprising: a mode selection circuit configured to generate a modeselection signal; and an output driver block configured to be connectedto an input/output pad and to transmit an output data signal, theinput/output pad being terminated at the pad with one of a VSSQtermination, a VDDQ termination and a termination off mode based on themode selection signal, and the output driver block comprising aplurality of output driver circuits, and one of the plurality of outputdriver circuits being configured to selectively operate or not operateduring transmitting the output data signal based on the mode selectionsignal, wherein each of the plurality of output driver circuits hasdifferent topology suitable for different operation speed, the operationspeed selected from a group including a low speed operation, and a highspeed operation faster than the low speed operation.
 2. The input/outputinterface of claim 1, wherein the VSSQ termination has a terminationvoltage level of a ground voltage level and the VDDQ termination has atermination voltage level of a supply voltage level respectively.
 3. Theinput/output interface of claim 1, wherein the mode selection signal isconfigured to receive include operating frequency information forselecting one among a plurality of on-die termination (ODT) circuits. 4.The input/output interface of claim 3, wherein the mode selection signalis configured to select the termination off mode if the operatingfrequency information indicates the low speed operation.
 5. Theinput/output interface of claim 3, wherein the mode selection signal isconfigured includes information indicating to select the VDDQtermination if the operating frequency information indicates anintermediate speed operation which is faster than the low speedoperation but slower than the high speed operation.
 6. The input/outputinterface of claim 3, wherein the mode selection signal is configuredincludes information indicating to select the VSSQ termination if theoperating frequency information indicates the high speed operation. 7.The input/output interface of claim 3, wherein the mode selection signalis configured includes information indicating to select a first outputdriver circuit among the plurality of the output driver circuits if theoperating frequency information indicates the high speed operation,wherein a pull-up driver of the first output driver circuit comprises aNMOS transistor.
 8. The input/output interface of claim 3, wherein themode selection signal is configured includes information indicating toselect a second output driver circuit among the plurality of the outputdriver circuits if the operating frequency information indicates one ofan intermediate speed operation and the low speed operation, theintermediate speed operation being faster than the low speed operationand slower than the high speed operation, wherein a pull-up driver ofthe second output driver circuit comprises a PMOS transistor.
 9. Aninput/output interface for a memory device comprising: a mode selectioncircuit configured to generate a mode selection signal; a terminationcircuit configured to provide the input/output interface with one of aVSSQ termination, a VDDQ termination and a termination off mode inresponse to the mode selection signal; and an output driver blockconfigured to transmit a data output signal, the output driver blockbeing connected to an input/output pad and comprising a plurality ofoutput driver circuits, wherein one of the plurality of output drivercircuits is configured to selectively operate or not operate accordingto the mode selection signal, the mode selection signal indicating atermination type of the termination circuit, wherein each of theplurality of output driver circuits has different topology suitable fordifferent operation speed, the operation speed selected from a groupincluding a low speed operation, and a high speed operation faster thanthe low speed operation.
 10. The input/output interface of claim 9,wherein the VSSQ termination has a termination voltage level of a groundvoltage level and the VDDQ termination has a termination voltage levelof a supply voltage level respectively.
 11. The input/output interfaceof claim 9, wherein the mode selection signal is configured includesinformation indicating to receive operating frequency information forselecting one among a plurality of on-die termination (ODT) circuits.12. The input/output interface of claim 11, wherein the mode selectionsignal is configured includes information indicating to select thetermination off mode if the operating frequency information indicatesthe low speed operation.
 13. The input/output interface of claim 11,wherein the mode selection signal is configured includes informationindicating to select the VDDQ termination if the operating frequencyinformation indicates an intermediate speed operation, the intermediatespeed operation faster than the low speed operation and slower than thehigh speed operation.
 14. The input/output interface of claim 11,wherein the mode selection signal is configured includes informationindicating to select the VSSQ termination if the operating frequencyinformation indicates the high speed operation.
 15. The input/outputinterface of claim 11, wherein the mode selection signal is configuredincludes information indicating to select a first output driver circuitamong the plurality of the output driver circuits if the operatingfrequency information indicates the high speed operation, wherein apull-up driver of the first output driver circuit comprises a NMOStransistor.
 16. The input/output interface of claim 11, wherein the modeselection signal is configured includes information indicating to selecta second output driver circuit among the plurality of the output drivercircuits if the operating frequency information indicates one of anintermediate speed operation faster than the low speed operation andslower than the high speed operation, and the low speed operation,wherein a pull-up driver of the second output driver circuit comprises aPMOS transistor.
 17. An input/output interface circuit for a memorydevice comprising: a mode selection circuit configured to generate amode selection signal; a termination circuit configured to provide theinput/output interface with one of a VSSQ termination, a VDDQtermination and a termination off mode in response to the mode selectionsignal; and an output driver block connected to an input/output padincluding, a first output driver circuit configured to transmit a outputdata signal, the first output driver circuit including a NMOS pull-updriver;, and a second output driver circuit configured to transmit theoutput data signal, the second output driver circuit including a PMOSpull-up driver, wherein one of the first output driver circuit and thesecond output driver circuit is selected to transmit the output datasignal in response to the mode selection signal.
 18. The input/outputinterface of claim 17, wherein the VSSQ termination has a terminationvoltage level of a ground voltage level and the VDDQ termination has atermination voltage level of a supply voltage level respectively. 19.The input/output interface of claim 17, wherein the mode selectioncircuit is configured to receive operating frequency information forselecting one among a plurality of on-die termination (ODT) circuits.20. The input/output interface of claim 19, wherein the mode selectionsignal is configured includes information indicating to select the firstoutput driver circuit if the operating frequency information indicates ahigh speed operation.
 21. The input/output interface of claim 19,wherein the mode selection signal is configured includes informationindicating to select the second output driver circuit if the operatingfrequency information indicates one of a medium speed operation and alow speed operation.